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this datasheet contains new product information. myson technology reserves the rights to modify the product specification witho ut notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales of the product. 1/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology features general description block diagram ? compliant to pci bus interface v2.2. ? ieee802.3 and 802.3u compliant. ? high performance with pci bus master structure. ? programmable pci burst length for low cpu utili- zation rate. ? transmit packet queuing capability for higher per- formance. ? supports both full-duplex and half-duplex mode operation. ? supports both ieee802.3x and xon/xoff full duplex flow control method. ? contains separate transmit and receive fifos. ? supports magic packet and microsoft wake-up frame filtering. ? supports acpi and pci power management. ? supports cardbus stschg pin and status changed registers. the cis can be stored in the eeprom. ? supports up to 128k bytes boot rom or flash memory without external latch. ? autoload eeprom contents after power-on. ? programmable eeprom interface. ? 128 pin pqfp package. ? single 3.3v power supply. integrated fast ethernet controller MTD800 is a highly integrated fast ethernet controller for pci interface. the chip contains a pci interface block, two large fifos( each is 2kilobytes ) for transmit and receive dma, ieee802.3 and 802.3u compliant mac interface for mii connection. besides that, the chip has the built-in wake-up controller to perform acpi function, and the capability of sensing ieee 802.3x frame to support xon/xoff flow con- trol protocol. the chip also has eeprom and boo- trom interface for no glue logic board implementation. for cardbus application, MTD800 supports four status-changed registers, an interface for accessing cis which is stored in eeprom and stschg pin to reflect the general wake-up event. eeprom control logic boot rom interface tx fifo tx dma control rx dma control rx fifo cfg & csr pci interface ad[31:0] pciclk rst# inta# cbe3[3:0] idsel frame# irdy# trdy# devsel# stop# par req# gnt# tx mii interface mac protocol processor rx mii interface wake-up controller led control led registers pme# wakeup txd[3:0] txen txck crs col rxd[3:0] rxdv rxck rxer ioslate#
2/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 1.0 pin connection 2.0 pin descriptions name pin # i/o descriptions pci bus interface pciclk 124 i pciclk provides timing reference for the MTD800 related pci transac- tions. all pci signals except rst#,inta# and pme# are sampled on the rising edge of this clock. rst# 122 i when rst# is asserted, all output signals are put into tristate and all open drain pins are floated. this signal is asynchronous to pciclk and have to be asserted for at least 10 active pci clock cycles. ad[31:0] 1 - 6, 9, 10 13 -15 20 - 24, 34 - 38, 41 - 43 , 45 -52 i/o 32-bit multiplexed address and data bus. a bus transaction consists of an address phase followed by one or more data phases. during the first cycle in which the frame# is asserted, the ad[31:0] represents the address bus while it is considered as a data bus during subsequent cycles. 128 pin qfp test# brd3 brd2 brd1 brd0 brcs# brwr# brrd# ecs vss vdd wup/sgh ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 cbe0# ad8 ad9 ad10 vdd vss vss_m col crs rxer rxd3 rxd2 rxd1 rxd0 rxck vdd vss txen txd3 txd2 txd1 txd0 txck rxdv inta# rst# vdd pciclk vss gnt# req# pme# v d d _ m m d i o m d c p a u s e a c t e p s e l b y p a s s # v s s v d d v d d r s t o u t # i s o l a t e # v s s b r a 1 6 b r a 1 5 b r a 1 4 b r a 1 3 b r a 1 2 b r a 1 1 b r a 1 0 b r a 9 b r a 8 b r a 7 v s s v d d b r a 6 b r a 5 b r a 4 b r a 3 b r a 2 b r a 1 b r a 0 b r d 7 b r d 6 v s s _ m v d d _ m b r d 5 b r d 4 a d 3 1 a d 3 0 a d 2 9 a d 2 8 a d 2 7 a d 2 6 v d d v s s a d 2 5 a d 2 4 c e b 3 # i d s e l a d 2 3 a d 2 2 a d 2 1 v d d v d d v s s v s s a d 2 0 a d 1 9 a d 1 8 a d 1 7 a d 1 6 c b e 2 # f r a m e # i r d y # t r d y # d e v s e l # s t o p # p e r r # p a r c b e 1 # a d 1 5 a d 1 4 a d 1 3 a d 1 2 a d 1 1 MTD800 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
3/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology cbe#[3:0] 11, 25, 33, 44 i/o 4-bit multiplexed bus command and byte enables. during the address phase transaction, cbe is considered as bus command. on the data phase cycles, cbe represents the byte enable signals for pci data bus. idsel 12 i used as a chip select during access to the configuration registers frame# 26 i/o driven by MTD800 to indicate the start and duration of a transaction. the frame# is deasserted when the master is ready to complete the final data phase in the transaction. irdy# 27 i/o during a write transaction, the current bus master asserts irdy# to indicate that valid data is being driven onto the pci bus. during a read transaction, this signal is asserted to indicate that the master is ready to accept data from the selected target. wait states are inserted until both irdy# and trdy# are asserted. trdy# 28 i/o during a read transaction, the target asserts trdy# to indicate that valid data is being driven onto the pci bus. during a write transaction, this signal is asserted to indicate that the target is ready to accept data. trdy# is used in conjunction with irdy#. a data phase is completed on any clock when both irdy# and trdy# are asserted. devsel# 29 i/o asserted by MTD800 to indicate that the device has decoded the address as the target of current access. as an input, devsel# indicates whether any device on the bus has been selected. stop# 30 i/o asserted by MTD800 to disconnect any further transaction. as an input, devsel# indicates whether any device on the bus or bridge has termi- nated the transaction. inta# 121 o/d inta# is an asynchronous signal which is used to request an interrupt. par 32 i/o ensures even parity across ad[31:0] and cbe[3:0]. par is stable and valid for one clock after the address phase. during the data phase, par is stable and valid for one clock after either irdy#(write transaction) or trdy#(read transaction) is asserted. gnt# 126 i asserted by the pci bus arbiter to indicate that MTD800 has granted the bus control authority. req# 127 o/z asserted by MTD800 to signal bus arbiter that it needs the dedicated access to the pci bus. perr# 31 i/o perr# is asserted when a data parity error is detected. pme# 128 o/d an interrupt signal for the occurrence power management event. asserted by MTD800 to request a change in the device or system power state. network interface col 104 i collision signal. col is asserted high when phy detects a collision on the medium. this signal is asynchronous to txck or rxck. rxdv 120 i receive data valid. rxdv is asserted high by phy to indicate the incoming receive data rxd[3:0] is valid. this signal is synchronous to rxck. txck 119 i transmit clock. txck is a continuous clock that provides the timing refer- ence for the transfer of the txd[3:0] and txen signals. txd[3:0] 115 - 118 o transmit data signals. txd are driven by MTD800 and transits synchro- nously with respect to the txck. txen 114 o transmit data enable. txen is driven by MTD800 and transits synchro- nously with respect to the txck. rxck 111 i receive clock. rxck is a continuous clock that provides the timing refer- ence for the transfer of the rxd[3:0], rxdv and rxer. name pin # i/o descriptions
4/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology rxd[3:0] 107 - 110 i receive data signals. rxd are driven by phy and transit synchronously with respect to the rxck. rxer 106 i receive error signal. rxer is asserted high to indicate a coding error is detected by phy. this signal is synchronous to rxck. crs 105 i carrier sense signal. crs is asserted by phy when either the transmit or receive medium is non-idle. this signal is asynchronous to txck or rxck. mdc 100 o management data clock. mdc is sourced by the MTD800 to control the transfer of the mdio data. a 1.5k pull up resistor is required to connect to this pin. mdio 101 i/o management data input/output. a bi-directional data interface connected to phy. a 1.5k pull up resistor is required to connect to this pin. led status output led_act# 98 o activity led. this signal will drive the led light on when detecting activity on mii interface. a 510 ohm pull up resistor is required to connect to this pin. led_paus e# 99 o pause led. this signal will drive the led light on when detecting transmis- sion is paused under the condition of receiving a xon frame. bootrom/ eeprom interface ecs 56 o a chip select signal for the external eeprom. eeprom is used to provide the configuration data and ethernet address. a 100k pull-up resister is con- nected to this pin. brrd# 57 o bootrom read signal. read out the content of bootrom onto the memory support data bus. brwr# 58 o bootrom write signal. when flash memory is used, brwr# is asserted low to enable the write action. brcs# 59 o a chip select signal for the external eprom (bootrom) or flash memory. the bootrom contains codes that can be usually executed for a system boot function. brd0/eedi 60 i/o a multiplexed signal for bootrom data bit 0 and serial rom data input. brd1/eedo 61 i/o a multiplexed signal for bootrom data bit 1 and serial rom data output. brd2/eeck 62 i/o a multiplexed signal for bootrom data bit 2 and serial rom clock signal. brd[7:3] 70 - 69, 66 - 65, 63 i/o bootrom data bus from bit 3 to bit 7. bra[16:0] 89- 80, 77 - 71 o bootrom address bus from bit 0 to bit 16. misc. interface wakeup/ stschg 53 o/z wakeup pin/cardbus stschg pin. in pci application, this pin is the wakeup pin to signal the host system of an wakeup event happened. in card bus application, this pin is used as the stschg pin to signal the system of any status changed. this pin is enabled as stschg pin if the pme_enable bit of the power management control register is set and the fmr.gwake, fmr.wake are both set. bypass# 96 i eeprom bypass mode. when asserted low, the eeprom function will be dis- able. this is useful for testing purpose. for normal operation, it should be con- nected to vdd. name pin # i/o descriptions
5/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology epsel 97 i eeprom selection pin. epsel is to determine which type of eeprom is chosen. 93c46 is used when epsel connects to vss, while 93c66 is selected if epsel connects to vdd. isolate# 91 i isolation pin. this pin should connect to the pci stable power signal (vdd). when pci bus is in b3 state, the power signal becomes deas- serted, however the isolation pin is active. under this condition, the pcirst# and pciclk are ignored and all the pci output signals except pme# are isolated from the pci bus. rstout# 92 o reset output pin. a active-low pulse is generated when power-on or hardware reset is detected. the pulse width is 245us. the phy can use this output pin as its reset signal, then phy can avoid to keep being reset during d3 state. power supply & ground vdd_m, vss_m 67, 102 68, 103 p/g digital 3.3v power and ground for internal sram. vdd 7, 16, 17, 40, 54,64, 78, 93, 94, 112, 123 p digital 3.3v power supply. vss 8, 18, 19, 39, 55, 79, 90, 95, 113, 125 g digital ground. name pin # i/o descriptions
6/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 3.0 functional description 3.1 pci bus operation the peripheral component interconnect (pci) is a high-speed backplane in modern pc. the MTD800 uses the pci bus to communicate with the host cpu and main memory to achieve high performance network com- putation. the MTD800 is directly compatible with revision 2.2 of the pci local bus specification and supports a subset of the pci bus transactions. it contains i/o read/write, memory read/write and configuration read/ write operations. besides that, all kinds of termination cycle are also supported. the MTD800 is acting as a pci bus target when handshaking with the host, while operating as a pci bus initiator when communicating with the host memory. 3.2 dma transmit function the dma transmit function is responsible for fetching data from the host?s memory into the on-chip transmit fifo, and then signalling mac transmit interface to relay the transmitted data onto the network if the fullness of fifo reaches the predefined threshold. the structure for the data to be transmitted is described in a format of chained link list(see figure 3.1). descriptors that reside in the host memory act as pointers to these transmit buffers. the transmit descriptor format is shown as figure 3.2. it consists of four long words. the first two words contain the transmit frame status, frame length and the descriptor ownership information. the last two words are the address pointers for the current data buffer and the next descriptor. the bit field definition of the descriptor words are given in table 3.1 and table 3.2 respectively. note that the transmit buffer address are not necessary to be in alignment of longword while the descriptors address should be longword aligned. the own- ership of buffer is indicated in the ?own? bit of the first descriptor. when driver has completed the preparation of being transmitted packet, it sets the ?own? bit to represent the buffer that belongs to the MTD800, and demands MTD800 to fetch the buffer and the associated descriptor. after the packet has been transmitted onto the network, the MTD800 clears the ?own? bit and issues an interrupt to notify the driver that the buffer can be reused. meanwhile, the driver is able to acquire the transmit status by reading the ?tsw? in the first descriptor. the MTD800 also has an advanced feature to enhance the transmit performance by ?closing? the first descriptor early once the packet has been transferred into the fifo completely. descriptor 0 descriptor 1 descriptor 2 buffer 0 buffer 1 buffer 2 point to next descriptor figure 3.1 descriptor chained structure
7/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology aa bit symbol description 31 own owner: this bit is controlled by driver, when set, identifies that the descriptor is owned by the MTD800. when reset, indicates that the descriptor is owned by the host; driver must reset this bit when initializa- tion. 30 -13 - reserved transmit status word (tsw) 13 abort abort: this bit is set when the current transmitting packet is aborted due to the excessive collision or late collision, 12 csl carrier sense lost: when set, the carrier is lost during the transmission of packet. 11 lc late collision: this bit is set when late collision occurs. 10 ec excessive collisions: this bit is set when the successive collision count exceeds 16 or 256 and the transmitting packet will be aborted. 9 dfr deferred: when set, indicates that MTD800 has to defer while ready to transmit a frame because of carrier sense asserted. 8 hf heart-beat failure: this bit is only effective in 10base-t mode. when set, indicates a heartbeat collision check failure. 7- 0 ncr[7:0] collision retry count: this 8-bit counter indicates that the number of collisions have occurred. table 3.1 transmit descriptor 0 ( tdes0) figure 3.2 the transmit descriptor format o reserved tsw tcw tbs[10:0] tx data buffer start address next descriptor address pkts[10:0]
8/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 3.2 transmit descriptor 1 ( tdes1 ) 3.3 dma receive function the dma receive function is responsible for collecting the network nibble-stream into the on-chip receive fifo, and then transferring the data onto the host?s memory if the fullness of fifo reaches the predefined pci burst length. the data structure for the receive buffer is a forward-link buffer chain which is similar to the transmit buffer. descriptors that reside in the host memory act as pointers to these receive buffers. the descriptor format is shown as figure 3.3. it consists of four long words. the first two words contain the receive frame status, frame length and the descriptor ownership information. the last two words are the address pointers for the current data buffer and the next descriptor. the bit field definition of the descriptor words are given in table 3.3 and table 3.4 respectively. note that the receive buffers and descriptors address both should be longword aligned. at the beginning, the driver allocates a set of free buffers and makes the ownership of these buffers belong to the chip. the MTD800 starts to fetches the first descriptor into its internal registers. bit symbol description transmit configure word (tcw) 31 ic interrupt control: this bit supports for interrupt pacing. when set, indi- cates that MTD800 will issue interrupt after the packet has been transmit- ted. 30 eic early interrupt control: this bit supports for interrupt pacing. when set, indicates that MTD800 will issue interrupt after the packet has been transferred into the internal fifo. 29 ld last descriptor: when set, it means the pointed buffer contains the last segment of a frame. 28 fd first descriptor: when set, it means the buffer contains the first segment of a frame. in descriptor ring structure, each buffer is classified as follows : fd ld description 1 1 single buffer descriptor 1 0 first buffer descriptor, further buffer chained 0 1 chained buffer packet end 0 0 intermediate buffer. 27 crc crc append : when set, the MTD800 will generate a crc field to append to the transmitted packet. 26 pad pad control : when set, the MTD800 will automatically pad zero?s to the end of packet whose length is less than 64 bytes. 25 rtlc retry late collision : when set, the late collision will be considered as a normal collision and the MTD800 just increases a collision count instead of aborting the packet. 24 - 22 - reserved. 21 - 11 pkts[10:0] packet size : this field contains the length of the transmitted packet. the value should be valid for the first descriptor. the size is indicated in bytes. 10 - 0 tbs transmit buffer size : this field contains the size information of buffer. if the transmitted packet only use one single buffer, the tbs should be equal to pkts. the size is also indicated in bytes.
9/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology once the packet has arrived in, the received data can be immediately transferred onto the dedicated location of the host memory by means of the predefined address which contains in the third word of the descriptor. after the receive buffer has been filled up with the received packet, the MTD800 clears the ?own? bit in the descriptor and issues an interrupt to notify the driver that the data in the buffer are ready to be taken away. the MTD800 also has an advanced feature to boost the receiving process. that is so-called ?receive early interrupt? operation, which demands the driver to move the data earlier than the completion of receiving the whole packet. table 3.3 receive descriptor 0 (rdes0) bit symbol description 31 own owner : this bit is controlled by driver, when set, identifies that the descriptor is owned by the MTD800. when reset, indicates that the descriptor is owned by the host; driver must reset this bit when initializa- tion. 30 - 28 - reserved. 27 - 16 flng[11:0] frame length : indicates that the frame length of received packet. this field is valid only when the descriptor contains the last segment of a frame. receive status register 1( rsr1 ) 15 - reserved. 14 mar multicast address received : the MTD800 receives a multicast address packet. 13 bar broadcast address received : the MTD800 receives a broadcast address packet. 12 phy physical address received : the MTD800 receives a physical address packet. 11 fsd first descriptor : when set, indicates that the descriptor contains the first segment of a received frame. 10 lsd last descriptor : when set, indicates that the descriptor contains the last segment of a received frame. 9 - 8 - reserved. receive status register 0 ( rsr0) o rsr1 rsr0 rbs[10:0] rx data buffer start address next descriptor address flng[10:0] reserved figure 3.3 the receive descriptor format
10/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 3.4 receive descriptor 1 (rdes1) 3.4 network interface and mac protocol handler the network interface for transmit and receive function are both in a format of mii and ready for the intercon- nection to phy chip. the MTD800 defines a simple and efficient protocol for transforming the fifo data back and forth to a nibble-stream that is directly connected to mii. meanwhile, the built-in media access controller (mac), which is compliant to ieee 802.3, performs the following functions ; (i) transmit function : encapsulates the nibble-stream coming from transmit dma with preambles, start frame delimiter (sfd), the frame check sequence and the padding zeroes if necessary; (ii) receive function : delimits the incoming packet , extracts the destination address for recognition and checks frame validation before transferring data onto the internal receive fifo; (iii) csma/cd function : executes the listening before transmission, makes sure 96-bit time for interframe gap , detects collision and enforces the event by issuing jam pattern, enters into backoff state after collision and waits for retransmission . the mac of the MTD800 also supports full-duplex function and ieee 802.3x flow control protocol. if the incoming packet with the predefined flow control destination address ( .i.e. 01-80-c2-00-00-01 ) and length/ 7 es error summary: this bit is set to 1 for receive error, the errors include the following - runt packet error (runt), - long packet error (long) , - frame alignment error (fae), - crc error (crc), and - receive coding error (rxer). 6 runt runt packet received : when set, indicates the MTD800 receives a packet whose length is less than 64 bytes. 5 long long packet received : when set, indicates that the received frame length exceeds the maximum ethernet-specified size of 1518 bytes. 4 fae frame align error : when set, indicates that the received frame has an alignment error. 3 crc crc error : when set, indicates a crc error occurred on the received frame. 2 rxer receive error : when set, indicates a receive coding error occurred on the received frame. 1 - 0 - reserved bit symbol description 31 - 11 - reserved 10 - 0 rbs receive buffer size : receive buffer size for this descriptor, the size is measured in bytes. the buffer size must be a multiple of 4. bit symbol description
11/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology type field ( .i.e. 88-08 ), the mac detects to receive the flow control packet and then pauses the transmission process after the completion of the current transmitted packet. the mac continues to transmit packets after the pause-time has expired. on the other hand, the mac can automatically send out a flow control packet once the fullness of receiving fifo has reached a predefined threshold to prevent the fifo from overflowing and rendering packet loss. 3.5 eeprom and bootrom interface the MTD800 uses eeprom to store configuration data, ethernet and wake-up-lan address etc. for card- bus application, the cis can also be saved in the eeprom. the bootrom contains the codes for executing a system boot function. since eeprom and bootrom share some i/o pins, these two devices can not be ena bled at the same time. 3.5.1 eeprom contents for desktop pci application, the MTD800 only use 12 words to store configuration and address information. therefore, an eeprom with the size of 64 x 16 bits ( i.e., 93c46 ) is enough to convey the data for such an application. however, in the system of cardbus, it needs more space to save cis data and usually a large size of eeprom ( e.g. 93c66 ) is required. the memory map of eeprom and the bit field description for configuration words are shown in the following tables.
12/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 3.5 eeprom memory map note: (1) the above figure shows the layout of serial eeprom which takes the size of 4k bits. (2) the low order byte of the first word contains the pointer to the last word of implementation specific area. in this case, the value is ?10h?. for different implementation, the area can be extended to ?3fh? in maximum. (3) the high order byte of the first word will be written as ?73h? if the eeprom has been programmed. (4) the card bus cis data are stored in the range addressed from 280h to 3ffh. the address is an offset from memory base address. the cis can only be accessed from memory address space. table 3.6 bit-field description of the configuration words offset d15 d8 d7 d0 offset from mem base 00h 73h last word pointer 200h 01h cfg 0 202h 02h cis pointer 1 cis pointer 0 204h 03h cis pointer 3 cis pointer 2 206h 04h max_lat min_gnt 208h 05h subsystem id1 subsystem id 0 20ah 06h subsystem vendor id1 subsystem vendor id0 20ch 07h reserved reserved 20eh 08h ethernet address 1 ethernet address 0 210h 09h ethernet address 3 ethernet address 2 212h 0ah ethernet address 5 ethernet address 4 214h 0bh reserved reserved 216h 0ch wake-up lan address 1 wake-up lan address 0 218h 0dh wake-up lan address 3 wake-up lan address 2 21ah 0eh wake-up lan address 5 wake-up lan address 4 21ch 0fh reserved reserved 21eh 10h cfg 2 cfg 1 220h 11h reserved reserved 12h | 3fh reserved for future use 222h | 27eh 40h | ffh used for card bus information tuples 280h | 3ffh bit symbol description configuration register 0 7 pmc power management capability. corresponding to bit 4 of cfsr. 6 ndfa not defined flow control address. corresponding to bit 12 of rcr.
13/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 3.5.2 direct programming of eeprom the MTD800 features a easy way to program external eeprom in-suit. when the reset is active and if the upper byte of 00h on eeprom is not 73h, the sromps bit in csr40 register will be cleared to indicate that the current eeprom has not been programmed yet. this allows the MTD800 to enter into direct program- ming mode if dpm bit is also set. in this mode the user can directly control the eeprom interface signals by writing to the srom_cr port and the value on the eecs, esk and edi bits will be driven onto the ecs, eeclk( brd2) and eedi( brd0) outputs respectively. these outputs will be latched so the user can gener- ate a clock on eeclk by repetitively writing 1 then 0 to the appropriate bit. this can be used to generate the eeprom signals as per the 93c46 or 93c66 data sheet. to read out the eeprom data, users have to generate eeprom interface signals into ecs, eeclk and eedi as described above and in the mean time read the data from eedo( brd1 ) input via pin brd1/eedo. reading data transfer port during programming will not affect the latched data on ecs, eeclk and eedi outputs. when the eeprom has been programmed and verified ( remember to program the upper byte of 00h with 73h), the user can give MTD800 a power-on reset to return to normal operation or set autold bit to read in the new data. the direct programming mode is mainly used for production to program every bit of the blank eeprom. the MTD800 also provides a flexible feature to allow the driver to reprogram the content of eeprom, even the eeprom has already been programmed. 3.5.3 bootrom interface and operation 5 tfcen transmit flow control packet enable. corresponding to bit 8 of tcr 4 - 2 brsz[2:0] indicates the boot rom size. corresponding to bit 28 -26 of brom_cr. 1 - 0 brspd[1:0] boot rom speed select. corresponding to bit 25 - 24 of brom_cr. configuration register 1 7 rfcen receive flow control packet enable. corresponding to bit 13 of rcr. 6 pme pme_enable. when set, indicates that the chip can assert wake-up event pin. corresponding to bit 8 of cfpmr. 5 psd3c pme support d3cold. corresponding to bit 31 of cfpmr. 4 psd1 pme support d1. corresponding to bit 28 of cfpmr. 3 wpp wake-up pin property. when set, the wake-up pin is asserted high, while cleared, the wake-up pin is asserted low. 2 - reserved. 1 mpe magic packet enable. corresponding to bit 1 of wuecsr. 0 stschg status change enable. when set, the stschg pin is active, otherwise it acts as a wake-up pin. configuration register 2 7 - 2 - reserved. 1 wppn wake-up pin pattern. when set, the wake-up output pin is a level signal, while cleared, the wake-up output pin is a pulse signal with the width of 160ms. 0 - reserved. bit symbol description
14/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology the MTD800 offers the address , data and control signals which can directly connected to bootrom without external logic on board. the bootrom size and speed can be configured beforehand and stored in the eep- rom. the access time ranges from 120ns to 300ns and the size achieves to 128kbytes at a maximum are all feasible to the MTD800. during machine boot, the system software identifies bootable devices by search- ing a specific signature (55aa) in bootrom. once found, the system copies the code from the bootrom to a shadow ram in the host memory and executes the code from the ram. 3.6 wake-up frame controller and acpi the MTD800 is compliant to acpi specification by providing d0/d1/d3cold power states and a wake-up mechanism to transit from lower power state to higher power state. when the MTD800 enters into d1 power down state, only the pci configuration registers can be accessed and other circuits except mac and wake-up controller are all disabled to save power. the most saving power state is under the d3cold condition. in this state, all power to the pci interface is cut off and the pci clock is stopped, and requires an auxiliary power source to maintain mac and wake-up controller to work normally. once the MTD800 receives a wake-up packet, the chip will issue a pme# interrupt to notify system to be back to the d0 state or assert wakeup sig- nal to atx power ps-on(refer to atx specification v2.01) or mother board?s wake up interrupt line like ring-in to power on the whole system. the wake-up frame controller supports the capabilities of recognizing amd magic packet frame and microsoft onnow network device wake-up frames. the magic packet is defined by the amd for using to wake up the system during the powerdown session. this packet contains a special pattern which is composed by 16 dupli- cations of wake-up lan address. in general, the address is the ieee address of this node. this pattern can be located anywhere within the packet, but must be preceded by a synchronization stream which is defined as 6 bytes of ffh. meanwhile, a network wake-up frame is typically a frame that is sent by existing network pro- tocols. there are arp request frame, unicast ip frame, direct ipx frame, netbios name-lookup frame and so on. each protocol has its own signature pattern. a network frame filter is designed to check the received frame if the signature pattern is embedded or not. the filter is parameterized with the byte offset, byte mask, crc-16 and filtering commands. the MTD800 supports two such filters which are defined in the command and status registers ( i.e., csr4c, csr50, csr54 and csr58 ). 4.0 registers description 4.1 pci configuration space the operation of pci configuration enables a full software-driven initialization and configuration. this permits the software to identify and query the MTD800. for keeping the contents of configuration registers intact after power-up, a software reset has no effect on them. there are total 15 long-word configuration registers. of the configuration registers, 13 are standard registers that are defined in the pci local bus specification, while the other 2 are MTD800-specific registers. following is the structure of configuration registers.
15/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 4.1 pci configuration space for mtd 800 4.1.1 id registers - (cfvid , cfdid, cfrid, cfsvid, cfsid) table 4.2 some pci identification registers 31:24 24:16 15:8 7:0 00h device id vendor id 04h status command 08h class code revision id 0ch reserved latency timer cache line size 10h base address register ( i/o map) 14h base address register ( memory map) 18h - 24h reserved 28h cardbus cis pointer 2ch subsystem id subsystem vendor id 30h expansion rom base address register 34h reserved capabilities pointer 38h reserved 3ch max_lat min_gnt interrupt pin interrupt line 40h remote wake- up-lan addr. 4 remote wake- up-lan addr. 3 remote wake- up-lan addr. 2 remote wake- up-lan addr. 1 44h reserved remote wake- up-lan addr. 6 remote wake- up-lan addr. 5 48h - 84h reserved 88h power management capabilities next item pointer capabilities identification 8ch reserved power management control & status
16/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.1.2 command register - ( cfcr) the command register is located at configuration address of 04h. a value of 0 in cfcr means that the device is logically isolated from pci bus for all access except con- figuration cycle. table 4.3 bit definition of the command register name location width description vendor id 00h 16-bit this field is hardwired to 1516h this field indicates the device is manufactured by myson. the valid identification is unique and allocated by the pci sig. device id 02h 16-bit this field is hardwired to 800h this register identifies the one of the devices manufactured by myson. the value is allocated by myosn. revision id 08h 8-bit this field is hardwired to 00h this register specifies that the device?s revision identifier. subsystem vendor id 2ch 16-bit the value is 00h after hardware reset at final state, this field is loaded from eeprom. this regis- ter provides an identification to identify the add-in card is manufactured by which one of subsystem house, although they has the same pci controller. its value can be allocated by pci sig. subsystem id 2eh 16-bit the value is 00h after hardware reset. at final state, this field is loaded from eeprom. this regis- ter is subsystem vendor specific to identify the add-in card. name field description io space bit 0 the value is 0 after hardware reset. this bit is readable and writable. a value of 1 allows the device to response an io access. otherwise, a value of 0 disables the device to echo. memory space bit 1 the value is 0 after hardware reset. this bit is readable and writable. a value of 1 allows the device to response memory transaction. otherwise, a value of 0 disables the device to echo. bus master bit 2 the value is 0 after hardware reset. this bit is readable and writable. a value of 1 enables the device?s master function, else a value of 0 disables the function.
17/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.1.3 status register - 06h (cfsr) the status register is located at the configuration address of 06h. table 4.4 bit definition of the status register reserved bit 3 this field is hardwired to 0. memory write and invalidate bit 4 the value is 0 after hardware reset. this bit is readable and writable. a value of 1 allows the device to generate memory write and invalidate command, else a value of 0 prohibits generating the command. reserved bit 5 this field is hardwired to 0. parity error response bit 6 the value is 0 after hardware reset. this bit is readable and writable. a value of 1 allows the device to take a normal action, like asserting perr_, when parity error is detected. otherwise it ignores the detection and continues to oper- ate. reserved bit 7~15 this field is hardwired to 0. name field description reserved bit 0~3 this field is hardwired to 0. power manage- ment capability bit 4 the value of this field is loaded from eeprom. a value of 1 indicates that power management function is imple- mented in the device. and it meets the requirement of pci bus power management interface specification. reserved bit 5~6 this field is hardwired to 0. fast back-to-back capable bit 7 this field is hardwired to 1. a value of 1 indicates the device is able to accept the operation of fast back-to-back which is activated by different masters. name field description
18/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.1.4 burst register ( cfbr) table 4.5 the contents of burst registers 4.1.5 base address register data parity error detected bit 8 the value is 0 after hardware reset. this field is read only and write-one to clear. this bit is set when three conditions are true concurrently. (1) the device asserts perr_ itself or it detects asserted perr_. (2) the device is as a bus master during a operation in which a error occurred. (3) the parity error response bit is set. devsel_ timing bit 9~10 this field is hardwired to 01h. a value of 01h indicates the device asserts devsel_ with medium speed. reserved bit 11 this field is hardwired to 0. received target abort bit 12 the value is 0 after hardware reset. this field is read only and write-one to clear. this bit is set when- ever the device?s master detects a termination with target abort. received master abort bit 13 the value is 0 after hardware reset. this field is read only and write-one to clear. this bit is set when- ever the devices?s master terminates the transaction with master abort. reserved bit 14 this field is hardwired to 0. detected parity error bit 15 the value is 0 after hardware reset. this field is read only and write-one to clear. this bit is set when- ever the device detects a parity error. name field description
19/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology there are three base address registers. they are located at configuration address of 10h, 14h and 30h respectively. following are the descriptions of these registers. table 4.6 i/o map base address register ( cfiobr ) table 4.7 memory map base address register ( cfmbr ) name location width description cache line size 0ch 8-bit the value is 00h after hardware reset. this field is readable and writable. this register specifies the cache line size for one burst. all of memory write and inval- idate, memory read line and memory read multiple cache- oriented commands must transfer data in a burst limited by cache line size. the chip only supports cls of 8, 16 and 32 longwords. if an attempt is made to write an unsupported value to this register, the chip behaves as if a value of zero was written. latency timer 0dh 8-bit the value is 00h after hardware reset. this field is readable and writable. this register limits the maximum time in which the device is permitted to access the bus. min_gnt 3eh 8-bit the value is 0 after hardware reset. at final state, this field is loaded from eeprom. this regis- ter indicates how long the device needs to convey the data in a burst . it is in a unit of 0.25us max_lat 3fh 8-bit the value is 0 after hardware reset. at final state, this field is loaded from eeprom. this regis- ter indicates how often the device needs to convey the data. it is in a unit of 0.25us. name field description io space indicator bit 0 this field is hardwired to 1. a value of 1 indicates that the register presents io base address reserved bit 1 this field is hardwired to 0. io space size bit 2~6 this field is hardwired to 0. these bits are hardwired to 0 to indicate the device requires io space in size of 128 longwords. io base address bit 7~31 the value is 0 after hardware reset. these bits is readable and writable. this field can be programmed by bios to specify the base address.
20/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 4.8 expansion rom base address register ( cferbr ) 4.1.6 cardbus cis pointer register - 28h, 32-bit width.(cfcispr) the cardbus cis pointer register is located at the configuration address of 28h. table 4.8 the content of cardbus cis pointer register name field description memory space indicator bit 0 this field is hardwired to 0. the value of 0 indicates that the register presents memory base address reserved bit 1~3 this field is hardwired to 0. memory space size bit 4~9 this field is hardwired to 0. these bits are hardwired to 0 to indicate the memory space size that the device requires. memory base address bit 10~31 a value is 0 after hardware reset. these bits is readable and writable. this field can be programmed by bios to specify the base address. name field description address decode enable bit 0 the value is 0 after hardware reset. this field is readable and writeable.this bit is set to 1 if the device requires the expansion rom space, else it is set to 0. after the load- ing of rom size from eeprom, the value is set 1 if the rom size is not equals to zero, reserved bit 1~10 this field is hardwired to 0. expansion rom size and base address bit 11~31 the value is 0 after hardware reset. this field is partitioned to two parts, one is for size and another is for base address. size field is hardwired to 0 dependent on rom size. base address field is read-write bits which can be allocated by bios.
21/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.1.7 interrupt register ( cfir ) table 4.8 the content of interrupt register 4.1.8 class code register ( cfccr ) table 4.8 the content of class code register 4.1.9 capabilities pointer register ( cfcpr ) table 4.9 the content of capabilities pointer register name field description address space indicator bit 0~2 the value is 0 after hardware reset. this field is read only and loaded from eeprom. these bits indi- cate the location of cis base address. (1) the value of 2 indicates that the cis is stored in eeprom (2) the value of 7 indicates that the cis is stored in expansion rom. address space off- set bit 3~27 the value is 0 after hardware reset. this field is read only and loaded from eeprom. these bits con- tains the address offset within the address space indicated by the address space indicator. rom image bit 28~31 the value is 0 after hardware reset. this field is read only and loaded from eeprom. the 4-bit rom image field value when the cis is in an expansion rom. name location width description interrupt line 3ch 8-bit the value is 0 after hardware reset. these bits is readable and writable. this field contains the routing information of system interrupt controller. interrupt pin 3dh 8-bit this field is hardwired to 01h. the value of 01h indicates the device uses inta_ to interrupt.
22/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.1.10 wake-up-lan / power management registers ( cfwuar, cfpmr ) the wake-up-lan register stores the address for matching the magic packet under power-down mode and locates at the configuration address of 40h and 44h. the power management register defines the asso- ciated control and status bits with the power management event and octets at the configuration address of 88h and 8ch. when the chip works in power down mode, these two registers can not be accessed. any read or write action is ignored during d1/d3hot states. table 4.10 the content of wake-up-lan / power management registers name location description class codes 09h ~ 0bh this field is hardwired to 020000h. the value of 020000h indicates the device is a ethernet controller. name location description capabilities pointer 34h this register stores a pointer to the power-management register block in the pci configuration space. this pointer is in effect only when the power management capabilities bit in the status register is set. otherwise, the pointer is set to ?00h?. the value of this field is ?88h? when power-management bit is set. name field description remote wake-up-lan address register ( offset 40h ) wul_addr3 31 - 24 the 4th byte in the wake-up-lan address. the value is loaded from eeprom. wul_addr2 23 - 16 the 3rd byte in the wake-up-lan address. the value is loaded from eeprom. wul_addr1 15 - 8 the 2nd byte in the wake-up-lan address. the value is loaded from eeprom. wul_addr0 7 - 0 the 1st byte in the wake-up-lan address. the value is loaded from eeprom. ( offset 44h ) reserved 31 - 16 this field is hardwired to 0. wul_addr5 15 - 8 the 6th byte in the wake-up-lan address. the value is loaded from eeprom. wul_addr4 7 - 0 the 5th byte in the wake-up-lan address. the value is loaded from eeprom.
23/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology power management block ( offset 88h) pme support d3cold 31 if this bit is set, the chip asserts pme in d3cold power state. other- wise, the chip does not asset pme in this power state. the value is loaded from eeprom. pme support d3hot 30 this field is hardwired to 1. the chip dose support d3hot power state. pme support d2 29 this field is hardwired to 0. the chip dose not support d2 power state. pme support d1 28 if this bit is set, the chip asserts pme in d1 power state. otherwise, the chip does not asset pme in this power state. the value is loaded from eeprom. pme support d0 27 this field is hardwired to 0. the chip dose not support pme dur- ing power state d0. d2 support 26 this field is hardwired to 0. the chip dose not support d2 power state. d1 support 25 this field is hardwired to 1. the chip supports d1 power state. reserved 24 - 22 this field is hardwired to 0. device specific initialization 21 this field is hardwired to 0, indicating that the chip does not require a special initialization code sequence in order to be config- ured correctly. reserved 20 this field is hardwired to 0. power manage- ment event clock 19 this field is hardwired to 0, indicating that the chip does not rely on the presence of the cardbus clock in order to generate a pme. power manage- ment pci version 18 - 16 this field is hardwired to ?001?, indicating that the chip complies with revision 1 of the pci power management specification . next item pointer 15 - 8 this field is hardwired to 8?h00, indicating that this is the last item of the capability linked list. capabilities id 7 - 0 this field is hardwired to 8?h01, indicating that this is the power- management register block. power-management control and status register ( offset 8ch) pme_status bit 15 when set, indicates that the chip has detected a power-management event. this bit is cleared on power-up reset or by write 1. it is not modified by software reset. pme_enable bit 8 when set, indicates that the chip can assert wake-up event pin. this bit is cleared on power-up reset. the value of this field is loaded from eeprom. power state bit 1 - 0 the definition of the field values are 0 -d0, 1 - d1, 2 - not defined and 3 - d3cold. the field gets a value of 0 after power-up. name field description
24/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2 command and status registers the MTD800 command and status registers (csrs) are mapped into the host i/o or the host memory address space through the base addresses defined in the pci configuration registers. the csrs are quad- byte aligned, 32-bit long, and must be accessed using longword instructions with quadbyte-aligned addresses only. following is the word layout table for csrs. table 4.11 MTD800 internal command and status registers layout offset address operation 00 par3 par2 par1 par0 rw 04 - - par5 par4 rw 08 mar3 mar2 mar1 mar0 rw 0c mar7 mar6 mar5 mar4 rw 10 far3 far2 far1 far0 rw 14 - - far5 far4 rw 18 tcr rcr rw 1c bcr rw 20 transmit poll demand wo 24 receive poll demand wo 28 receive current word pointer ro 2c transmit list base address wo 30 receive list base address wo 34 interrupt status register rw 38 interrupt mask register rw 3c flow control high threshold flow control low threshold rw 40 brom_cr srom_cr mii management rw 44 tally counter crc tally counter mpa ro 48 tally counter tsr ro 4c filter a byte mask wo 50 filter a offset filter a cmd filter a crc-16 rw 54 filter b byte mask wo 58 filter b offset filter b cmd filter b crc-16 rw 5c wake-up events csr rw 78 tx fifo dump register ro 7c rx fifo dump register ro 80 function event register rw 84 function event mask register rw 88 function present state register ro 8c function force event register wo
25/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.1 physical address registers ( par ) these registers store the nic card?s ethernet physical address. the location of par is mapped into an offset address ranges from 00h to 05h. during the receiving process, the pre-stored physical node address is used for address recognition logic to filter out the incoming packets which are not belong to this addressed sta- tion. the physical address registers are loaded from eeprom during initialization and can also be changed by software driver when the chip is not during operation, but it remains unchanged after software reset is applied. note that the single-byte write is not supported to this register. 4.2.2 multicast address registers ( mar ) these registers store 64 bits serving as hash bucket heads. the location of mar is mapped into an offset address range from 08h to 0fh. for any incoming packet with a multicast destination address, the MTD800 applies the standard ethernet cyclic redundancy check (crc) function to the destination address field, then it uses the most significant 6 bits of the result as a bit index into the table. if the indexed bit is set, the frame is accepted. if the bit is cleared, the frame is rejected. the value in this register is undetermined after hardware reset and can not be changed by software reset. note that the single-byte write is not supported to this regis- ter. 4.2.3 flow-control address registers ( far ) these registers stores a special destination address for the flow control packet. the location of far is mapped into an offset address range from 10h to 15h. during full-duplex operation, the incoming packet?s da will be compared to this flow control address, if matched, then the chip will take the appropriate action. according to the ieee 802.3x standard, the contents of these address registers should be written with 01-80- c2-00-00-01 by driver. the value in this register is undetermined after hareware reset and can not be changed by software reset. note that the single-byte write is not supported to this register. 4.2.4 receive configuration register ( rcr ) this register is located in an offset address of 18h and the access type is read/writable. the receive configu- ration register reflects the nic receive configuration and can be cleared to the default value by hardware/soft- ware reset. following is the bit description of rcr. table 4.12 the content of receive configuration register
26/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology bit symbol description 15 rxs receive status. when ?1?, indicates the receive process is running. when ?0?, indicate the receive process is stopped. this is a read-only bit and the default value is ?0?. 14 eien early interrupt enable. when set, the chip will work under early interrupt mode. when cleared, it will operate in normal interrupt mode. the default value is ?0?. 13 rfcen receive flow control packet enable. when set, the flow control packet will be recognized during full duplex operation. when cleared, it will be considered as a normal packet. the default value is ?0?, but may be changed by loading from eeprom. 12 ndfa not defined flow control address. for the legacy flow control device, a 802.3x special da was not defined at that time. for the reason of back- ward compatibility, only the length/type field is checked when this bit is set. the default value is ?0?. 11 rblen receive burst length enable. when set, the receive burst transaction will use the following receive programmable burst length. when cleared, the pbl defined in the bus command register will be adopted. the default value is ?1?. 10- 8 rpbl[2:0] receive programmable burst length rpbl2 rpbl1 rpbl0 length 0 0 0 1 words 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 512 the default value is ?011?. 7 prom promiscuous mode bit. if prom equals to 1, all valid packets with any physical destination address are accepted. if prom equals to 0, the physical address of incoming packet must match the node address pro- grammed in the par0 ~ 5, otherwise it will be rejected. the default value is ?0?. 6 ab accept broadcast bit. if ab equals to 1, all packets with broadcast desti- nation address are accepted. if ab equals to 0, any packet with broadcast address is rejected. the default value is ?1?. 5 am accept multicast bit. if am equals to 1, all packets with desired multicast destination address are accepted. if am equals to 0, any packet with mul- ticast address is rejected. the default value is ?1?. 4 reserved. 3 arp accept runt packet. if arp equals to 1, all packets with their length less than 64 bytes are accepted. if arp equals to 0, any packet whose length is less than 64 bytes is rejected. the default value is ?0?.
27/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.5 transmit configuration register ( tcr ) this register is located in an offset address of 1ah and the access type is read/writable. the transmit configu- ration register reflects the nic transmit configuration and can be cleared to the default value by hardware or software reset. following is the bit description of tcr. table 4.13 the content of transmit configuration register 2 alp accept long packet. if alp equals to 1, all packets with their length larger than 1518 bytes are accepted. if alp equals to 0, any packet whose length is larger than 1518 bytes is rejected. the default value is ?0?. 1 sep set error packet. if sep equals to 1, all packets with receive errors are accepted. if sep equals to 0, any packet with receive errors is rejected. the default value is ?0?. 0 re receive enable. when set, the receive process enters into the running state. the MTD800 attempts to acquire a descriptor from the receive list and processes the incoming frame. when cleared, the receive process is placed in the stopped state after completing the reception of current frame. the default value is ?0?. bit symbol description 15 txs transmit status. when ?1?, indicates the transmit process is running. when ?0?, indicate the transmit process is stopped. this is a read-only bit and the default value is ?0?. 14-13 reserved 12 backopt optional backoff. when set, a non-standard algorithm will be used. the default value is ?0?. 11 fback fast back-off. when ?1?, indicates the back off algorithm will not count up to one slot time instead of one bit time. it will speed up the process of retransmitting data and mainly used for debugging. 10 - reserved 9 enhanced when set, the chip will work under enhanced mode, otherwise, a normal operation mode is selected. the default value is ?0?. 8 tfcen transmit flow control packet enable. when set, the chip is able to trans- mit the flow-control packet during full duplex operation. when cleared, it will not transmit any flow-control packet. the default value is ?0?, but may be changed by loading from eeprom. bit symbol description
28/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.6 bus command registers ( bcr ) the register is located in an offset address of 1ch. the access type of bcr is read/writable. the bus com- mand register is used to control the operation of pci bus transaction by means of adjusting the burst length or enabling the read/write cache commands. the register can be cleared to the default value by hardware or software reset. following are the bit description of bcr. table 4.14 the content of bus configuration register 7 - 5 tft[2:0] transmit fifo threshold tft2 tft1 tft0 threshold 0 0 0 64 bytes 0 0 1 32 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 768 1 1 0 1024 1 1 1 transmit store and forward the default value is ?000?. 4 fd full-duplex mode. the half-duplex operation is selected when fd is cleared, while the full-duplex operation is selected when fd is set. the default value is ?0?. 3 ps port speed. when auto-negotiation is enabled, this bit reflects the status of current connection speed. ?1? means 10mb/s while ?0? indicates as 100mb/s. the default value is ?0?. 2 te transmit enable. when set, the transmission process enters into the run- ning state, and the MTD800 checks the transmit list at the current position for a frame to be transmitted. when cleared, the transmission process is placed in the stopped state after the completion of the current frame transmission.the default value is ?0?. 1 - 0 lb[1:0] loopback mode selection. 0 0 normal 1 0 mii loopback the default value is ?00?. bit symbol description
29/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.7 transmit poll demand register ( txpdr) the txpdr is used for software driver to command MTD800 to poll the transmit descriptor list. this register is located at an offset address 20h and the access type is write only. table 4.15 transmit poll demand register bit symbol description 31- 10 - reserved 9 prog programming. this bit is totally controlled by driver and not affect the hardware operation. it is a tag bit for driver to differentiate the program- ming status when multiple cards installed in a platform. the default value is ?0?. 8 rle read line command enable. when set, this cache-oriented command will be used if cache-alignment occurs. the default value is ?0?. 7 rme read multiple command enable. when set, this cache-oriented com- mand will be used if cache-alignment occurs. the default value is ?0?. 6 wie write and invalidate command enable. when set, this cache-oriented command will be used if cache-alignment occurs. the default value is ?0?. 5 - 3 pbl programmable burst length. determines the allowable number of long- words to be transferred during one pci transaction initiated by the MTD800. there are eight permissible values used for burst length. the relationship between the value in pbl and burst length is shown below; pbl2 pbl1 pbl0 length 0 0 0 1 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 512. the default value is ?011?. 2 - 1 - reserved. 0 swr when set, the MTD800 resets all internal hardware except that the con- figuration registers and address registers like par, far and mar etc. are not affected. the default value is ?0?. bit symbol description 31 - 0 - when written with any value, the MTD800 begins to check the frame for transmission.
30/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.8 receive poll demand register ( rxpdr ) the rxpdr is used for software driver to command MTD800 to poll the receive descriptor list. this register is located at an offset address 24h and the access type is write only. table 4.16 receive poll demand register 4.2.9 receive current word pointer ( rxcwp ) the rxcwp allows the driver to read the current address value in the rx dma address counter register. this counter will keep the track of location in the host memory for the last moved-in received word. this register is useful when operates in the receive early interrupt mode. it must be cleared after hardware or software reset. the location of rxcwp is at an offset address 28h and the access type is read only. table 4.17 the content of receive current word pointer register 4.2.10 transmit list base address ( txlba ) the txlba stores the base address for the transmit descriptor list. this register is located at an offset address 2ch and the access type is read/writable. the base address is used for MTD800 to point to the start of the transmit descriptor list. it must be cleared after hardware or software reset and the access type is write only. table 4.18 transmit list base address register 4.2.11 receive list base address ( rxlba ) the rxlba stores the base address for the receive descriptor list. this register is located at an offset address 30h and the access type is read/writable. the base address is used for MTD800 to point to the start of the receive descriptor list. it must be cleared after hardware or software reset and the access type is write only. bit symbol description 31 - 0 - when written with any value, the MTD800 begins to check if any available descriptor for the reception. bit symbol description 31- 2 rxcwp indicates the current word pointer of received word in the host memory. 1-0 mbz this field must be zero since the address have to be longword alignment. bit symbol description 31- 2 ba indicates the base address that points to the start of the transmit list. 1-0 mbz this field must be zero since the descriptors have to be longword align- ment.
31/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 4.19 receive list base address register 4.2.12 interrupt status register ( isr ) the interrupt status register reflects the nic?s interrupt status. the host reads from this register to determine the cause of the interrupt. individual bit is cleared by writing a ?1? to the corresponding bit. it must be cleared after hardware or software reset. isr is located in an offset address of 34h. the access type are read/writa- ble. following is the bit description of the register. table 4.20 the content of interrupt status register bit symbol description 31- 2 ba indicates the base address that points to the start of the receive list. 1-0 mbz this field must be zero since the descriptors have to be longword align- ment. bit symbol description 31-18 - reserved. 17 rfcon receive flow control xon packet. when asserted, indicates that the flow control xon packet is received. 16 rfcoff receive flow control xoff packet. when asserted, indicates that the flow control xoff packet is received. 15 - 14 - reserved. 13 fbe fatal bus error. indicates that a bus error occurs. the type of error is shown in the following bits. 12 - 11 et error type. indicates the type of error that causes bus error. they are valid only when fbe is set. these two bits are read only. following is their definition, et1 et0 error type 0 0 parity error 0 1 master abort 1 0 target abort 1 1 reserved. 10 tunf transmit underflow. when asserted, indicates that the tx fifo underflow condition occurs during frame transmission. 9 rovf receive overflow. when asserted, indicates that the rx fifo overflow condition occurs during frame reception. 8 eti early transmit interrupt. indicate that the frame to be transmitted is fully transferred into the tx fifo but not transmitted onto the network. 7 eri early receive interrupt. indicates that the received packet has filled the first data buffer of the frame. 6 cntovf counter overflow. when asserted, indicates that crc or mpa tally coun- ter encounters overflow condition. 5 rbu receive buffer unavailable. when asserted, indicates that the next descriptor is owned by the host and cannot be acquired by the MTD800.
32/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.13 interrupt mask register ( imr ) the interrupt mask register is used for masking the interrupt which is reflected in the corresponding bit in the interrupt status register. after power up, all bits are reset to ? 0?. to set the individual bit will enable the corre- sponding interrupt. it must be cleared after hardware or software reset. imr is located in an offset addresses of 38h.the access type is read/writable. following is the bit description of the register. table 4.21 the content of interrupt mask register 4 tbu transmit buffer unavailable. when asserted, indicates that the next descriptor is owned by the host and cannot be acquired by the MTD800. 3 ti transmit interrupt. when asserted, indicates that the frame transmission has completed. 2 ri receive interrupt. when asserted, indicates that the frame reception has completed. 1 rxeri receive error interrupt. this bit takes effective only in the receive early interrupt mode. when set, indicates that the current received frame is erroneous. 0 - reserved. bit symbol description 31 - 18 - reserved. 17 mrfcon mask receive flow control xon packet. when set, the rfcon interrupt is masked. 16 mrfcoff mask receive flow control xoff packet. when set, the rfcoff interrupt is masked. 15 - 14 - reserved. 13 mfbe mask fatal bus error. when set, the fbe interrupt is masked. 12-11 - reserved. 10 mtunf mask transmit underflow. when set, the tunf interrupt is masked. 9 mrovf mask receive overflow. when set, the rovf interrupt is masked. 8 meti mask early transmit interrupt. when set, the eti is masked. 7 meri mask early receive interrupt. when set, the eri is masked. 6 mcntovf mask counter overflow. when set, the cntovf interrupt is masked. 5 mrbu mask receive buffer unavailable. when set, the rbu interrupt is masked. 4 mtbu mask transmit buffer unavailable. when set, the tbu interrupt is masked. 3 mti mask transmit interrupt. when set, the ti is masked. 2 mri mask receive interrupt. when set, the ri is masked. bit symbol description
33/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.14 flow control high / low threshold registers ( fcht / fclt ) the chip can generate a flow control pause frame ( here a xon frame ) when the fullness of its rx fifo is beyond the high threshold. after the data in the rx fifo have been consumed a lot, such that the fullness is below the low threshold, then a xoff frame is issued. these registers hold the high/low threshold value which determine the number of words left in the rx fifo. the contents of these registers can not be changed by software reset. the location of register is mapped to an offset address 3ch. table 4.22 the content of flow control threshold registers 4.2.15 bootrom / eeprom and mii management registers( brom_cr/srom_cr/ miimgt ) the brom_cr, srom_cr and miimgt registers provide an interface for the driver to access the boot rom, serial eeprom and the mii management port. they are respectively located at the offset address of 43h, 42h and 40h. brom_cr defines the boot rom size, speed and the control mode. srom_cr provides the direct programming mode for the driver to read and write the eeprom. the miimgt selects an operation mode for reading and writing the mii phy registers through the mii management interface. the register must be cleared to the default value after hardware or software reset except that the ?brwe? bit is not changed by software reset. table 4.23 the content of bootrom / eeprom and mii management registers 1 mrxeri mask receive error interrupt. when set, the rxeri is masked. 0 - reserved. bit symbol description 31-25 - reserved. 24-16 fcht flow control high threshold register. the default value is ?180h? after hardware reset. 15-9 - reserved. 8-0 fclt flow control low threshold register. the default value is ?80h? after hardware reset. bit symbol description brom_cr ( offset 43h ) 31 - 30 - reserved 29 brwe boot rom write enable. this bit is effective only when a flash memory is used instead of eprom. when set, a write operation will be executed. the default value is ?0? and can not be changed by software reset. bit symbol description
34/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 28 - 26 brsz[2:0] indicates the boot rom size. brsz[2] brsz[1] brsz[0] size 0 0 0 0 ( means no boot rom ) 0 0 1 8k bytes 0 1 0 16k bytes 0 1 1 32k bytes 1 0 0 64k bytes 1 0 1 128k bytes 1 1 x reserved. the default value is ?0? but may be changed by loading from eeprom. 25 - 24 brspd[1:0] boot rom speed select. brspd[1] brspd[0] access time 0 0 120 ns 0 1 180 ns 1 0 240 ns 1 1 300 ns the default value is ?0? but may be changed by loading from eeprom. srom_cr ( offset 42h ) 23 dpm direct programming mode. when set, it allows the driver to directly access eeprom. the default value is ?0?. 22 sromps serial eeprom programming status. this bit is read-only. when ?1?, indicates that the eeprom has been programmed. when ?0?, means that the eeprom is not programmed yet. the default value is ?0?. 21 - reserved. 20 autold auto load. when set, it allows the chip to dynamically reload eeprom contents. after auto-load completed, this bit will be self-cleared. the default value is ?0?. 19 ecs eeprom interface cs signal . this bit is effective only when direct pro- gramming mode is enabled. the default value is ?0?. 18 eck eeprom interface ck signal. this bit is effective only when direct pro- gramming mode is enabled. the default value is ?0?. 17 edi eeprom interface di signal. this bit is effective only when direct pro- gramming mode is enabled. the default value is ?0?. 16 edo eeprom interface do signal ( read-only). this bit is effective only when direct programming mode is enabled. the default value is ?0? but may be changed due to the pin value. miimgt ( offset 40h ) 15-4 - reserved 3 mout mdio output enable indicator while in direct programming mode. the default value is ?0?. 2 mdo mii management port data output status while in direct programming mode. the default value is ?0?. bit symbol description
35/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.16 tally counters for crc and mpa ( tc_crc / tc_mpa ) the tally counter crc is used to count the number of events that crc error occurs within the received packet, while the tally counter mpa accumulates the number of discarded frames because that the receive buffer is unavailable or the receive fifo overflows. these registers are located at the offset address of 44h and 46h respectively. the access type is read only and the content is cleared after read. the default value is 0 after hardware reset and can not be changed by software reset. table 4.24 the content of tally counters for crc and mpa 4.2.17 tally counters for transmit status report (tc_tsr) the tally counter tsr is used to count the number of events that the transmitting packet is aborted due to the excess collisions, the number of events that occurring late collision and the retry counts that ever happened. these registers are located at the offset address of 48. the access type is read only and the content is cleared after read.the default value is 0 after hardware reset and can not be changed by software reset. table 4.24 the content of tally counters for tsr 4.2.18 network wake-up frame configuration registers the MTD800 supports onnow network device class wake-up frames such as ip , ipx and snap frames. these registers are used to load the filtering parameters for matching the dedicated patterns which are embedded in each type of network frame. two filters are provided to check the incoming frames. each filter can operate in conjunction with another filter to recognize a frame with complicated patterns. filter a is located at an offset address 4ch while the filter b is mapped to an offset of 54h. both are in the same format 1 mdi mii management port data input status while in direct programming mode ( read-only). the default value is ?0? but may be changed due to the pin value. 0 mdc mii management port clock status while in direct programming mode. the default value is ?0?. bit symbol description 31 tcovf when set, indicates that crc tally counter overflows. 30 - 16 crc_c indicates the number of events that crc error occurs. 15 tmovf when set, indicates that mpa tally counter overflows. 14 - 0 mpa_c indicates the number of discard frame because of buffer unavailable or fifo overflow. bit symbol description 31- 24 abort_c indicates the number of aborted packets. 23 - 16 lcol_c indicates the number of late collisions. 15 - 0 ncr indicates the number of transmission retry. bit symbol description
36/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology and can be read/writable. the contents of these registers is cleared to the default value after hardware reset but can not be changed by software reset. table 4.25 fileter byte mask ( a : offset 4ch , b : offset 54h ) table 4.26 filter offset, command and crc-16 ( a : offset 54h , b : offset 5c ) 4.2.19 wake-up events control and status register ( wuecsr ) the wuecsr stores the control bits for commanding the ability of wake-up operation and the status bits for monitoring the occurrence of wake-up events. this register is located at an offset address 5ch and the access type is read/writable. the register can be cleared to the default value after hardware or software reset. table 4.27 the content of wake-up events control and status register bit symbol description 31 - reserved 30 - 0 bm[30:0] byte mask. when bm[i] is set, it allows the ith byte to be checked. when bm[i] is reset, the filter will not do any operation on the ith byte. the default value is ?0?. bit symbol description 31 - 24 bo[7:0] byte offset. indicates the offset position from the first byte of frame to be examined by the filter. the minimum value allowed for this field is ?12? in decimal. the default value is ?12? in decimal. filter command 23 - 19 - reserved 18 conj conjuction. when set, a logic and operation will be performed on the result of previous filter and the current one. when cleared, the matching result of each filter is independent. the default value is ?0?. 17 iom inverse operation mode. when set, the frames which satisfy the dedi- cated pattern will be reject. it renders that the frame dose not match the filter considered as a network wake-up frame. the default value is ?0?. 16 fe filter enable. when set, the filtering parameters are only effective, other- wise, the filter is disabled. the default value is ?0?. 15 - 0 crc16 this field contains the 16-bit crc value which is calculated according to the dedicated pattern specified by the offset and byte-mask. he default value is ?0?. bit symbol description 31 - 12 - reserved. 11 frcwup force wake up lan mode. when set, the chip is forced to receive only magic packet or wake-up frame under d0 state. it is useful for debugging purpose. the default value is ?0?. 10 stschg status change enable. when set, the stschg pin is active, otherwise it acts as a wake-up pin. the default value is ?0? but may be changed by loading from eeprom.
37/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 4.2.20 tx/rx fifo dump registers these two registers are used for internal test only. when transmit or receive process is stopped, the driver can directly access these dump registers for debugging purpose. 4.2.21 cardbus status changed registers for complying to cardbus specification, the chip implements four status changed registers. these registers are accessed by the cardbus system software and typically not reached by the MTD800 driver. the status changed registers are mapped only to the memory space and not to the i/o space. the four registers take effect to the operation of chip only when the ?stschg? bit of the eeprom is set. note that the unspecified bits in the following register should be hardwired to zero. 9 agu accept global unicast. when set, any unicast packet accepted by the MTD800 will be considered as a wake-up event. the default value is ?0?. 8 wppn wake-up pin output pattern. when set, the wake-up output pin is a level signal, while cleared, the wake-up output pin is a pulse signal with the width of 160ms. the default value is ?1? but may be changed by loading from eeprom. 7 wpp wake-up pin property. when set, the wake-up pin is asserted high, while cleared, the wake-up pin is asserted low. the default value is ?1? but may be changed by loading from eeprom. 6 - reserved. 5 mpr magic packet received. when set, indicates that a wake-up event is gen- erated by the reception of magic packet.it is cleared by writing 1 to this bit.the default value is ?0?. 4 wufr wake-up frame received. when set, indicates that a wake-up event is generated by the reception of wake-up frame.it is cleared by writing 1 to this bit.the default value is ?0?. 3 - 2 - reserved. 1 mpe magic packet enable. a 1 enables the wake-up event due to the recep- tion of magic packet while a 0 disables this function. the default value is loaded from eeprom. 0 wufe wake-up frame enable. a 1 enables the wake-up event due to the reception of wake-up frame while a 0 disables this function. the default value is ?0?. bit symbol description
38/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology table 4.28 the content of cardbus status changed registers 1. function event register 2. function event mask register 3. function preset state register 4. function force event register bit symbol description 15 interrupt this bit is set in response to interrupt pending. it is cleared by write one. 4 gwue general wake-up event. when the chip has detected a power manage- ment event, this bit is set accordingly. this bit is also automatically cleared upon that the pme_status bit in the configuration register is reset. it is cleared by write one. bit symbol description 15 inten interrupt enable. when set, enables the assertion of the card bus inter- rupt pin. 14 wuesen wake-up event summary enable. when set together with the general wake-up event enable bit, allows the assertion of the stschg pin. 4 gwueen general wake-up event enable. when set together with the wake-up event summary enable bit, allows the assertion of the stschg pin. bit symbol description 15 intsts interrupt status. this bit reflects the status of interrupt line. 4 gwue general wake-up event. this bit reflects the current state of the wake-up event. bit symbol description 15 frceint force interrupt. the interrupt pin is asserted by writing 1 to this bit, but the interrupt bit in function present register is not affected. 4 frcewu force wake-up. the stschg pin is asserted by writing 1 to this bit, but the wake-up event field in the function present register is not affected.
39/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 5.0 electrical characteristics 5.1 dc characteristics 5.1.1 absolute maximum ratings 5.1.2 recommended operating conditions 5.1.3 dc electrical characteristics 5.2 ac characteristics 5.2.1 mii timing symbol parameter rating unit v cc power supply voltage -0.3 to 3.6 v v in input voltage -0.3 to vcc+0.3 v v out output voltage -0.3 to vcc+0.3 v t stg storage temperature -55 to 150 o c symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 - vcc v t opr commercial junction operating temperature 0 25 115 o c industrial junction operating temperature -40 25 125 o c symbol parameter conditions min. typ. max. unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -1 1 ua c in input capacitance 2.8 pf c out output capacitance 2.7 4.9 pf c bid3 bi-direction buffer capacitance 2.7 4.9 pf v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v oh output high voltage i ol =2,4,8,12,16,24ma 2.4 v v ol output low voltage i oh =2,4,8,12,16,24ma 0.4 v r i input pull-up/down resistance v il =0v or v ih =v cc 75 kohm
40/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 5.2.2 pci timing ? read cycle symbol parameter min. typ. max. unit note t1 mii input setup time 10 ns t2 mii input hold time 10 ns t3 mii output setup time 20 35 ns t4 mii output hold time 5 20 ns rxc crs,rxd txc txen txd rxdv t1 t2 t3 t4 valid valid pciclk frame# ad{31:0] cbe#[3:0] irdy# devsel# trdy# address data read cmd byte enable t1 t2
41/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology ? write cycle symbol parameter min. typ. max. unit note t1 pci clk cycle time 30 40 ns t2 clk to signal valid delay 2 11 ns t3 input setup time to clk 7 ns t4 input hold time to clk 0 ns pciclk frame# ad{31:0] cbe#[3:0] irdy# devsel# trdy# address data write cmd byte enable t3 t4
42/42 MTD800 revision 0.0 07/20/1999 mtd 800 (preliminary) myson technology 6.0 package dimension 6.1 128 pin pqfp 103 128 1 38 39 64 65 102 seating plane see detail a a a 1 a 2 e b d 1 d e 1 e l l1 z detail a note: 1.dimension d1 & e1 do not include mold protrusion. but mold mismatch is included. allowable protrusion is .25mm/.010? per side. 2.dimension b does not include dambar protrusion. allowable dambar protru- sion .08mm/.003?. total in excess of the b dimemsion at maximum material condition. dambar cannot be located on the lower radius or the foot. 3.controlling dimension : millimeter. symbol dimension in inch dimension in mm min norm max min norm max a - - 0.134 - - 3.40 a1 0.010 - - 0.25 - - a2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.50 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 z 0 o - 7 o 0 o - 7 o y see detail b detail b c b with plating base metal gage plane

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